1. Field of The Invention
The present invention relates generally to a semiconductor integrated circuit device which has a well having the same conductive type as that of a substrate and being pn-separated from the substrate and which has various gate insulator films having different thickness, and a method for producing the same. More specifically, the invention relates to a technique for reducing the number of masks for use in the production of the semiconductor integrated circuit device.
The present invention also relates generally to a semiconductor integrated circuit device including two kinds of transistors having the same conductive channel. More specifically, the invention relates to a method for producing a semiconductor integrated circuit device, which forms wells for element regions by ion implantation before forming an element isolating insulator film.
2. Related Background Art
A typical CMOS semiconductor integrated circuit device has an n-type well for forming a p-channel MOSFET (which will be hereinafter referred to as a xe2x80x9cPMOSxe2x80x9d), and a p-type well for forming an n-channel MOSFET (which will be hereinafter referred to as an xe2x80x9cNMOSxe2x80x9d).
Some of such typical CMOS semiconductor integrated circuit devices have a well which is pn-separated from a substrate and which has the same conductive type as that of the substrate. For example, there is a semiconductor integrated circuit device wherein an NMOS, in which a back gate potential is the same as the potential of a p-type substrate, and an NMOS, in which a back gate potential is different from the potential of the p-type substrate, are integrated on the single p-type substrate. In the case of such a semiconductor integrated circuit device, a p-type well pn-separated from the p-type substrate is formed, and an NMOS, in which the back gate potential is different from the p-type substrate, is formed in the p-type well.
FIG. 72 is a sectional view of a semiconductor integrated circuit device having a p-type well which is pn-separated from a p-type substrate. FIGS. 73(A) through 73(E) are profile diagrams showing the distribution of an impurity in a substrate, wherein FIG. 73(A) shows a profile along line 73Axe2x80x9473A in FIG. 72, FIG. 73(B) showing a profile along line 73Bxe2x80x9473B in FIG. 72, FIG. 73(C) showing a profile along line 73Cxe2x80x9473C in FIG. 72, FIG. 73(D) showing a profile along line 73Dxe2x80x9473D in FIG. 72, and FIG. 73(E) showing a profile along line 73Exe2x80x9473E in FIG. 72.
However, in a process for producing a semiconductor integrated circuit device having a p-type well pn-separated from a p-type substrate, it is required to add a photolithography step of forming the p-type well pn-separated from the p-type substrate, to a typical process for producing a semiconductor integrated circuit device. Therefore, the number of masks for use in the photolithography step increases, so that the manufacturing costs increase.
As the prior art of the present invention, a method for producing the semiconductor integrated circuit device shown in FIG. 72 will be described below.
FIGS. 74(A) through 74(C), 75(A) through 75(C) and 76(A) and 76(B) are sectional views showing principal steps of producing the semiconductor integrated circuit device shown in FIG. 72.
First, as shown in FIG. 74(A), an element isolating region 102 is formed on the surface of a p-type silicon substrate 101 by the LOCOS method to define divided element regions 103 on the surface of the substrate 101. Then, the surface of the (silicon) substrate 101 exposed to the element regions 103 is, e.g., thermally oxidized, to form buffer oxide films 104 on the surfaces of the element regions 103. FIGS. 77(A) through 77(E) show impurity profiles in the substrate 101 after the buffer oxide films 4 are formed. FIG. 77(A) shows a profile along line 77Axe2x80x9477A in FIG. 74(A), FIG. 77(B) showing a profile along line 77Bxe2x80x9477B in FIG. 74(A), FIG. 77(C) showing a profile along line 77Cxe2x80x9477C in FIG. 74(A), FIG. 77(D) showing a profile along line 77Dxe2x80x9477D in FIG. 74(A), and FIG. 77(E) showing a profile along line 77Exe2x80x9477E in FIG. 74(A). As shown in FIGS. 77(A) through 77(E), after the buffer oxide films 4 are formed, the conductive impurities in the substrate 101 are only p-type impurities originally contained in the substrate 101.
Then, as shown in FIG. 74(B), a photoresist is applied on the substrate 101 to form a photoresist film 105. Then, holes 106a, 106b are formed in the photoresist film 105 by the photolithography method. The hole 106a is formed so as to correspond to a region wherein an n-type well is formed, and the hole 106b is annularly formed so as to surround a region wherein a pxe2x88x92-type well separated from the substrate 101 is formed. Then, using the photoresist film 105 as a mask, an n-type impurity 107 is ion-implanted into the substrate 101. Thus, an n-type well 108-1, and an n-type well 108-2 surrounding a region, in which the pxe2x88x92-type well separated from the substrate 101 is formed, are simultaneously formed. FIGS. 77(F) through 77(J) show impurity profiles in the substrate 1 after the n-type wells 108-1 and 108-2 are formed. FIG. 77(F) shows a profile along line 77Fxe2x80x9477F in FIG. 74(B), FIG. 77(G) showing a profile along line 77Gxe2x80x9477G in FIG. 74(B), FIG. 77(H) showing a profile along line 77Hxe2x80x9477H in FIG. 74(B), FIG. 77(I) showing a profile along line 77Ixe2x80x9477I in FIG. 74(B), and FIG. 77(J) showing a profile along line 77Jxe2x80x9477J in FIG. 74(B). As shown in FIGS. 77(F) through 77(J), the n-type impurity 107 is introduced so that the density thereof is higher than that of the p-type impurity originally contained in the substrate 101, to form the n-type wells 108-1 and 108-2 in the substrate 101.
Then, as shown in FIG. 74(C), after the photoresist film 105 is removed from the substrate 101, a photoresist is applied again to form a photoresist film 109. Then, a hole 110 is formed in the photoresist film 109 by the photolithography method. The hole 110 is formed so as to correspond to a region wherein a pxe2x88x92-type well connected to the substrate 101 is formed. Then, using the photoresist film 109 as a mask, an n-type impurity 111 is ion-implanted into the substrate 101. Thus, an embedded n-type well 112 apart from the surface of the substrate 101 is formed in a region surrounded by the n-type well 108-2 of the substrate 1. FIGS. 78(A) through 78(E) show impurity profiles in the substrate 101 after the n-type well 112 is formed. FIG. 78(A) shows a profile along line 78Axe2x80x9478A in FIG. 74(C), FIG. 78(B) showing a profile along line 78Bxe2x80x9478B in FIG. 74(C), FIG. 78(C) showing a profile along line 78Cxe2x80x9478C in FIG. 74(C), FIG. 78(D) showing a profile along line 78Dxe2x80x9478D in FIG. 74(C), and FIG. 78(E) showing a profile along line 78Exe2x80x9478E in FIG. 74(C). As shown in FIGS. 78(A) through 78(E), the n-type impurity 111 is introduced so that the density thereof is higher than that of the p-type impurity originally contained in the substrate 1, to form the embedded n-type well 112 in the substrate 101.
Then, as shown in FIG. 75(A), after the photoresist film 109 is removed from the substrate 101, a photoresist is applied again to form a photoresist film 113 thereon. Then, holes 114-1 and 114-2 are formed in the photoresist film 113 by the photolithography method. The hole 114-1 is formed so as to correspond to a region wherein a pxe2x88x92-type well connected to the substrate 101 is formed, and the hole 114-2 is formed so as to correspond to a region wherein pxe2x88x92-type well pn-separated from the substrate 101 is formed. Then, using the photoresist film 113 as a mask, a p-type impurity 115 is ion-implanted into the substrate 101. Thus, a pxe2x88x92-type well 116-1 is formed in the substrate 101, and a pxe2x88x92-type well 116-2 is formed in a region surrounded by the n-type well 108-2 of the substrate 101. The pxe2x88x92-type well 116-1 is connected to the substrate 101, and the pxe2x88x92-type well 116-2 is pn-separated from the substrate 101. FIGS. 78(F) through 78(J) show impurity profiles in the substrate 1 after the pxe2x88x92-type wells 116-1 and 116-2 are formed. FIG. 78(F) shows a profile along line 78Fxe2x80x9478F in FIG. 75(A), FIG. 78(G) showing a profile along line 78Gxe2x80x9478G in FIG. 75(A), FIG. 78(H) showing a profile along line 78Hxe2x80x9478H in FIG. 75(A), FIG. 78(I) showing a profile along line 78Ixe2x80x9478I in FIG. 75(A), and FIG. 78(J) showing a profile along line 78Jxe2x80x9478J in FIG. 75(A). As shown in FIGS. 78(F) through 78(J), the p-type wells 116-1 and 116-2 are formed by adding the p-type impurity to the originally p-type substrate 101, so that the p-type wells 116-1 and 116-2 have a higher density of p-type impurity than that of the substrate 101.
Then, as shown in FIG. 75(B), the photoresist film 113 is removed from the substrate 101.
Then, as shown in FIG. 75(C), the buffer oxide films 4 are removed. Thus, the surface of the substrate 101 (the surface of each of the n-type well 108-1 and the pxe2x88x92-type wells 116-1, 116-2 in this embodiment) is exposed to the element regions 103.
Then, as shown in FIG. 76(A), the surface of the substrate 101 exposed to the element regions 3 is thermally oxidized to form a gate oxide film 117.
Then, as shown in FIG. 76(B), a conductive film serving as a gate electrode of a transistor, e.g., a laminated film of a polycrystalline silicon and tungsten silicide film, is formed on the structure shown in FIG. 76(A). Then, the laminated film is patterned to form a gate electrode 118. Then, in accordance with a well-known method, a p-type impurity for forming a p-type source/drain is ion-implanted into the n-type well 108-1 to form a p-type source region 119S and a p-type drain region 119D. Then, in accordance with a well-known method, an n-type impurity for forming an n-type source/drain is ion-implanted into the pxe2x88x92-type wells 116-1 and 116-2 to form n-type source regions 120S-1, 120S-2 and n-type drain regions 120D-1, 120D-2.
Then, as shown in FIG. 72, an interlayer insulator film 121 of, e.g., a CVD oxide film, is formed on the structure shown in FIG. 76(B). Then, contact holes 122, which are communicated with the p-type source/drain regions 119S, 119D and the n-type source/drain regions 120S-1, 120D-1, 120S-2, 120D-2, respectively, are formed in the interlayer insulator film 121. Then, a conductive film serving as a wiring, e.g., an aluminum film, is formed. The aluminum film thus formed is patterned to form a wiring 123.
In such a producing method, it is required to carry out a photolithography step when the n-type wells 108-1 and 108-2 are formed (FIG. 74(B)), when the n-type well 112 is formed (FIG. 74(C)), and when pxe2x88x92-type wells 116-1 and 116-2 are formed (FIG. 75(A)). In particular, the step of forming the n-type well 112 shown in FIG. 74(C) is peculiar to the semiconductor integrated circuit device shown in FIG. 72. For that reason, when the semiconductor integrated circuit device shown in FIG. 72 is produced, the number of photolithography steps increases, and the number of masks for use in the photolithography steps increases. Therefore, the manufacturing costs increase in comparison with usual semiconductor integrated circuit devices.
In order to reduce the cost of producing the semiconductor integrated circuit device shown in FIG. 72, there is another producing method as follows.
FIG. 79 is a sectional view of a semiconductor integrated circuit device produced by another producing method. FIGS. 80(A) through 80(D) are profile diagrams showing the distribution of an impurity in a substrate. FIGS. 80(A) through 80(D) are profile diagrams showing the distribution of an impurity in a substrate, wherein FIG. 80(A) shows a profile along line 80Axe2x80x9480A in FIG. 79, FIG. 80(B) showing a profile along line 80Bxe2x80x9480B in FIG. 79, FIG. 80(C) showing a profile along line 80Cxe2x80x9480C in FIG. 79, and FIG. 80(D) showing a profile along line 80Dxe2x80x9480D in FIG. 79.
This producing method will be described below.
FIGS. 81(A) through 81(C), 82(A) and 82(B), and 83(A) and 83(B) are sectional views showing principal steps of producing the semiconductor integrated circuit device shown in FIG. 79.
First, as shown in FIG. 81(A), the surface of a p-type silicon substrate 101 is, e.g., thermally oxidized, to form a buffer oxide film 104 on the surface of the substrate 101. Then, a photoresist is applied on the buffer oxide film 104 to form a photoresist film 105. Then, holes 106a, 106b are formed in the photoresist film 105 by the photolithography method. The hole 106a is arranged so as to correspond to a region wherein an n-type well is formed, and the hole 106b is arranged so as to correspond to a region wherein a pxe2x88x92-type well separated from the substrate 101 is formed. Then, using the photoresist film 105 as a mask, an n-type impurity 107 is ion-implanted into the substrate 101. Thus, an n-type impurity injecting regions 108-1, and 108-2 are obtained. FIGS. 84(A) through 84(D) show impurity profiles in the substrate 101 after the n-type impurity 107 is ion-implanted. FIG. 84(A) shows a profile along line 84Axe2x80x9484A in FIG. 81(A), FIG. 84(B) showing a profile along line 84Bxe2x80x9484B in FIG. 81(A), FIG. 84(C) showing a profile along line 84Cxe2x80x9484C in FIG. 81(A), and FIG. 84(D) showing a profile along line 84Dxe2x80x9484D in FIG. 81(A). As shown in FIGS. 84(A) through 84(D), the n-type impurity 107 is injected so that the density thereof is higher than the density of the p-type impurity originally contained in the substrate 101.
Then, as shown in FIG. 81(B), after the photoresist film 105 is removed, a photoresist is applied again to form a photoresist film 113. Then, holes 114-1, 114-2 are formed in the photoresist film 113 by the photolithography method. The hole 114-1 is arranged so as to correspond to a region wherein a pxe2x88x92-type well connected to the substrate 101 is formed, and the hole 114-2 is arranged so as to correspond to a region wherein a pxe2x88x92-type well pn-separated from the substrate 101 is formed. Then, using the photoresist film 113 as a mask, a p-type impurity 115 is ion-implanted into the substrate 101 and the injecting region 108-2. Thus, p-type impurity injecting regions 116-1, 116-2 are obtained. FIGS. 84(E) through 84(H) show impurity profiles in the substrate 101 after the p-type impurity 115 is ion-implanted. FIG. 84(E) shows a profile along line 84Exe2x80x9484E in FIG. 81(B), FIG. 84(F) showing a profile along line 84Fxe2x80x9484F in FIG. 81(B), FIG. 84(G) showing a profile along line 84Gxe2x80x9484G in FIG. 81(B), and FIG. 84(H) showing a profile along line 84Hxe2x80x9484H in FIG. 81(B). As shown in FIGS. 84(E) through 84(H), the p-type impurity 115 is injected so as to have a higher density and shallower than the n-type impurity 107 contained in the injecting region 108-2.
Then, as shown in FIG. 81(C), the photoresist film 113 is removed. Then, heat treatment is carried out to diffuse/activate the n-type impurity of the injecting regions 108-1, 108-2 and the p-type impurity of the injecting regions 116-1, 116-2. Thus, the injecting regions 108-1, 108-2 become n-type wells 108-1, 108-2, respectively, and the injecting regions 116-1, 116-2 become pxe2x88x92-type wells 116-1, 116-2, respectively. FIGS. 84(I) through 84(L) show impurity profiles in the substrate 101 after the heat treatment is carried out. FIG. 84(I) shows a profile along line 84Ixe2x80x9484I in FIG. 81(C), FIG. 84(J) showing a profile along line 84Jxe2x80x9484J in FIG. 81(C), FIG. 84(K) showing a profile along line 84Kxe2x80x9484K in FIG. 81(C), and FIG. 84(L) showing a profile along line 84Lxe2x80x9484L in FIG. 81(C). As shown in FIG. 84(I) through 84(L), the p-type well 116-2 is particularly formed only in the n-type well 108-2 and pn-separated from the substrate 101.
Then, as shown in FIG. 82(A), an element isolating region 102 is formed on the surface of the substrate 101 to define divided element regions 103.
Then, as shown in FIG. 82(B), the buffer oxide film 4 is removed. Thus, the surface of the substrate 101 (the surface of each of the n-type well 108-1 and the pxe2x88x92-type wells 116-1, 116-2 in this embodiment) is exposed to the element regions 103.
Then, as shown in FIG. 83(A), the surface of the substrate 101 exposed to the element regions 3 is thermally oxidized to form a gate oxide film 117.
Then, as shown in FIG. 83(B), a conductive film serving as a gate electrode of a transistor, e.g., a laminated film of a polycrystalline silicon and tungsten silicide film, is formed on the structure shown in FIG. 83(A). Then, the laminated film is patterned to form a gate electrode 118. Then, in accordance with a well-known method, a p-type impurity for forming a p-type source/drain is ion-implanted into the n-type well 108-1 to form a p-type source region 119S and a p-type drain region 119D. Then, in accordance with a well-known method, an n-type impurity for forming an n-type source/drain is ion-implanted into the pxe2x88x92-type wells 116-1 and 116-2 to form n-type source regions 120S-1, 120S-2, 120D-1, 120D-2.
Then, as shown in FIG. 79, an interlayer insulator film 121 of, e.g., a CVD oxide film, is formed on the structure shown in FIG. 83(B). Then, contact holes 122, which are communicated with the p-type source/drain regions 119S, 119D and the n-type source/drain regions 120S-1, 120D-1, 120S-2, 120D-2, respectively, are formed in the interlayer insulator film 121. Then, a conductive film serving as a wiring, e.g., an aluminum film, is formed. The aluminum film thus formed is patterned to form a wiring 123.
According to such another producing method, the n-type well 108-1, the pxe2x88x92-type well 116-1 connected to the substrate 101, and the pxe2x88x92-type well 116-2 pn-separated from the substrate 102 can be formed by two photolithography steps shown in FIGS. 81(A) and 81(B). Therefore, it is possible to reduce the number of photolithography steps and the number of masks for use in photolithography steps.
However, in order to form the pxe2x88x92-type well 116-2 in the n-type well 108-2, the dose of the p-type impurity 115 injected in the step shown in FIG. 81(B) must be set to be higher than the impurity density of then-type well 108-2. That is,the amount of the p-type impurity 115 for forming the pxe2x88x92-type wells 116-1, 116-2 is rate-controlled by the impurity density of the n-type well 108-2. Therefore, there is no degree of freedom in the setting of the impurity density of the pxe2x88x92-type wells 116-1 and 116-2.
In addition, although the gate insulator film of a typical semiconductor integrated circuit device usually has one thickness, some of semiconductor integrated circuit devices have various gate insulator films having different thickness. A device of this type is used as, e.g., a semiconductor integrated circuit device wherein a plurality of potentials are applied to a gate of a MOSFET, or the like.
In such a semiconductor integrated circuit device, it is required to carry out a photolithography step in order to obtain various gate insulator films having different thickness. Therefore, the number of masks for use in the photolithography step increases, and the manufacturing costs increase as described above.
As described above, in a semiconductor integrated circuit device having an n-type well, a p-type well connected to a substrate, and a p-type pn-separated from the substrate, there is a problem in that the number of photolithography steps increases and the manufacturing costs increase.
In addition, although there is a method for producing a semiconductor integrated circuit device of this type without increasing the number of photolithography steps, there is a problem in that this method is difficult to freely set the impurity density of a p-type well.
Moreover, in a semiconductor integrated circuit device having various gate insulator films having different thickness, there is a problem in that the number of photolithography steps increases and the manufacturing costs increase.
By the way, most of semiconductor integrated circuits comprise different kinds of transistors. For example, a non-volatile semiconductor memory device, wherein a high voltage must be applied in the writing/erasing in a memory cell, uses a high-voltage transistor, to which a high voltage is applied, in addition to a low-voltage transistor for use in a logic circuit. The high-voltage transistor needs an element region having a lower impurity density than that of an element region for the low-voltage transistor, because of limitations of junction resistance and substrate bias characteristics.
Therefore, for example, when a p-type semiconductor substrate is used, a low-voltage n-channel MOS transistor and a low-voltage p-channel MOS transistor are formed in p-type and n-type wells formed by ion implantation, respectively, and a high-voltage n-channel MOS transistor is formed by using the p-type substrate, in which no well is formed, as an element region as it is.
When the p-type semiconductor substrate is used, the p-type and n-type wells are usually formed by ion implantation after forming an element isolating insulator film. In addition, the circuit region of the high-voltage transistor has a lower impurity density than that of the well region, so that it needs to have a p-type element isolating layer below the element isolating insulator film in order to insure element isolation. The applicant has proposed a technique for forming a p-type element isolating layer, which serves to isolate a high-voltage transistor, at the same time that the ion implantation step for forming the p-type well for a low-voltage transistor is carried out (Japanese Patent Application No. 9-44243).
FIG. 97 shows an example that low-voltage p-channel MOS transistors QP1, QP2, low-voltage n-channel MOS transistors QN1, QN2, and high-voltage n-channel MOS transistors QN3, QN4 are formed on a pxe2x88x92-type silicon substrate 1 by a conventional method. An element isolating insulator film 202 is formed by, e.g., the shallow trench isolation (STI) technique, before forming an n-type well 203 and a p-type well 204. That is, a groove is formed in the substrate 201, and the element isolating insulator film 202 is embedded in the groove by the CVD.
After forming the element isolating insulator film 202, ion implantation is carried out to sequentially form the n-type well and the p-type well 204. Directly below the element isolating film 202 adjacent to the high-voltage transistors QN3 and QN4, a p-type element isolating layer 205 is formed by ion implantation simultaneously with the ion implantation process for the p-type well 204.
FIG. 98 shows the ion implantation process for the p-type well 204 and the p-type element isolating layer 205 after forming the element isolating insulator film 202. As shown in the drawing, a resist mask 206 having openings 207a, 207b is patterned in a region wherein the p-type well 204 and the p-type element isolating layer 205 should be formed, by the lithography, and ion implantation is carried out. Since this ion implantation serves to form an impurity layer more deeply than the bottom of the element isolating insulator film 202, ion implantation at a high acceleration voltage is utilized.
As described above, in a conventional method for simultaneously forming a p-type well for a low-voltage transistor circuit and a p-type element isolating layer in a high-voltage transistor circuit region having a lower impurity density than that of the p-type well for the low-voltage transistor circuit after forming an element isolating insulator film, there is the following problem.
As shown in FIG. 98, the ion implantation for the p-type well 204 is carried out via the wide opening 207a including the element region for the n-channel MOS transistors QN1, QN2 and the element isolating region adjacent thereto, whereas the ion implantation for the p-type element isolating layer 205 in the element isolating region adjacent to the high-voltage n-channel MOS transistors QN3, QN4 is carried out via the narrow opening 207b. However, there is usually a step between the element isolating insulator film 202 and the substrate surface of the element region. Because the STI technique carries out the formation of a groove and the embedding of an element isolating insulator film while an element region is covered with a mask (not shown) of a silicon nitride film or the like, and then, removes the mask from the element region. Since such a step exists, it is not easy to form the resist mask 206 having the fine opening 207b at the lithography step.
In addition, in the method for carrying out ion implantation after forming the element isolating insulator film 202, the thickness of the resist must be great in order to obtain a sufficient mask effect for ion implantation since a high acceleration voltage is used. Thus, it is difficult to form the fine opening using the lithography. For these reasons, it is difficult to provide excellent element isolation characteristics in a low impurity density region when the element is scaled down.
Moreover, in the conventional method for forming the well after forming the element isolating insulator film 202, the depths of the element region and element isolating region in the p-type well 204 and n-type well 203 are different from each other as shown in FIGS. 97 and 98. This difference in depth corresponds to the height of the element isolating insulator film 202 projecting from the substrate surface of the element region. Therefore, the lateral resistance of the well increases by the substantial decrease of the thickness of the well in the element isolating region. Consequently, it is difficult to provide a constant potential in the whole well.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor integrated circuit device, which has a well having a conductive type different from that of a substrate, a well having the same conductive type as that of the substrate and being connected to the substrate, and a well having the same conductive type as that of the substrate and being pn-separated from the substrate and which can inhibit the increase of the number of photolithography steps and reduce the manufacturing costs while maintaining the advantage of capable of freely setting the impurity density of wells having the same conductive type as that of the substrate, and a method for producing the same.
It is another object of the present invention to provide a semiconductor integrated circuit device which has various gate insulator films having different thickness and which can suppress the increase of the number of photolithography steps and reduce the manufacturing costs, and a method for producing the same.
It is a further object of the present invention to provide a semiconductor integrated circuit device, which has a well having a conductive type different from that of a substrate, a well having the same conductive type as that of the substrate and being connected to the substrate, a well having the same conductive type as that of the substrate and being pn-separated from the substrate, and various gate insulator films having different thickness and which can inhibit the increase of the number of photolithography steps and reduce the manufacturing costs while maintaining the advantage of capable of freely setting the impurity density of wells having the same conductive type as that of the substrate, and a method for producing the same.
It is a still further object of the present invention to provide a semiconductor integrated circuit device having good element isolating characteristics, and a method for producing the same.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor integrated circuit device comprises: a semiconductor substrate of a first conductive type; a first semiconductor region which is formed on the semiconductor substrate and which includes an impurity of a second conductive type; a second annular semiconductor region which is formed on the semiconductor substrate and which includes an impurity of the second conductive type; a third embedded semiconductor region which is formed in a region surrounded by the second annular semiconductor region and which includes an impurity of the second conductive type; a fourth embedded semiconductor region which is formed on the semiconductor substrate and which includes an impurity of the second conductive type; a fifth semiconductor region which is formed above the third embedded semiconductor region and which includes an impurity of the first conductive type; a sixth semiconductor region which is formed above the fourth embedded semiconductor region and which includes an impurity of the first conductive type; and a transistor formed in the first, fifth and sixth semiconductor regions.
In the semiconductor integrated circuit device with the above described construction, the fourth embedded semiconductor region including the impurity of the second conductive type is arranged below the sixth preferred embodiment including the impurity of the first conductive type. Consequently, the mask used for introducing the impurity of the first conductive type for forming the fifth and sixth semiconductor regions can be in common with the mask used for introducing the impurity of the second conductive type for forming the third and fourth embedded semiconductor regions. Therefore, in the semiconductor integrated circuit device having the well (the first semiconductor region) having different conductive type from that of the substrate, the well (the sixth semiconductor region) which has the same conductive type as that of the substrate and which is connected to the substrate, the well (the fifth semiconductor region) which has the same conductive type as that of the substrate and which is pn-separated from the substrate, it is possible to suppress the increase the number of photolithography steps.
In addition, the fifth semiconductor region of the first conductive type is formed above the third semiconductor region of the second conductive type so as to correspond to the region surrounded by the second annular semiconductor region of the second conductive type. Consequently, the impurity density can be freely set without being under the influence of the semiconductor region of the second conductive type. Therefore, it is possible to maintain the advantage in that the impurity density of the well (the fifth and sixth semiconductor regions) of the same conductive type as that of the substrate can be freely set.
According to another aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: preparing a semiconductor substrate of a first conductive type; introducing an impurity of a second conductive type, which serves to form a first semiconductor region of the second conductive type and a second annular semiconductor region of the second conductive type, into the semiconductor substrate using a first mask; introducing an impurity of the second conductive type, which serves to form third and fourth embedded semiconductor regions of the second conductive type, into the semiconductor substrate and a region surrounded by the second annular semiconductor region using a second mask; introducing an impurity of the first conductive type, which serves to form fifth and sixth semiconductor regions of the first conductive type, into regions above the third and fourth semiconductor regions using the second mask; and forming a transistor in the first, fifth and sixth semiconductor regions.
According to another aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: forming a first gate insulator film on a semiconductor substrate; introducing a first impurity, which serves to form a first semiconductor region, into the semiconductor substrate using a first mask; introducing a second impurity, which serves to form a second semiconductor region, into the semiconductor substrate using a second mask; removing the first gate insulator film using the second mask; forming a second gate insulator film in a portion, from which the first gate insulator film has been removed, and increasing the thickness of a portion of the first gate insulator film, in which the first gate insulator film has been left; and forming a transistor using the first gate insulator film, and a transistor using the second gate insulator film.
In the above described method for producing the semiconductor integrated circuit device, the same mask (the second mask) is used for introducing the second impurity for forming the second semiconductor region and for removing the first gate insulator film. Therefore, in the semiconductor integrated circuit device having various gate insulator films having different thickness, it is possible to suppress the increase of the number of photolithography steps.
According to another aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: forming a first gate insulator film on a semiconductor substrate; introducing a first impurity, which serves to form a first semiconductor region, into the semiconductor substrate using a first mask; introducing a second impurity, which serves to form a second semiconductor region, into the semiconductor substrate and a region, into which the first impurity has been introduced, using a second mask; removing the first gate insulator film using the second mask; forming a second gate insulator film in a portion, from which the first gate insulator film has been removed, and increasing the thickness of a portion of the first gate insulator film, in which the first gate insulator film has been left; and forming a transistor using the first gate insulator film, and a transistor using the second gate insulator film.
According to another aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: forming a first gate insulator film on a semiconductor substrate; introducing a first impurity, which serves to form a first semiconductor region, into the semiconductor substrate using a first mask; introducing a second impurity, which serves to form a second semiconductor region, into the semiconductor substrate using a second mask; introducing a third impurity, which serves to form a third semiconductor region, into the semiconductor substrate, a region, into which the first impurity has been introduced, and a region, into which the second impurity has been introduced, using a third mask; removing the first gate insulator film using the third mask; forming a second gate insulator film in a portion, from which the first gate insulator film has been removed, and increasing the thickness of a portion of the first gate insulator film, in which the first gate insulator film has been left; and forming a transistor using the first gate insulator film, and a transistor using the second gate insulator film.
According to another aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: forming a first gate insulator film on a semiconductor substrate of a first conductive type; introducing a first impurity of a second conductive type, which serves to form a first semiconductor region of the second conductive type and a second annular semiconductor region of the second conductive type, into the semiconductor substrate using a first mask; introducing a second impurity of the second conductive type, which serves to form third, fourth and fifth embedded semiconductor regions of the second conductive type, into the semiconductor substrate, a region surrounded by the second annular semiconductor region, and a region, into which the first impurity has been introduced, using a second mask; introducing a third impurity of the first conductive type, which serves to form sixth, seventh and eighth semiconductor regions of the first conductive type, into regions above the third, fourth and fifth semiconductor regions, using the second mask; removing the first gate insulator film using the second mask; forming a second gate insulator film in a portion, from which the first gate insulator film has been removed, and increasing the thickness of a portion of the first gate insulator film, in which the first gate insulator film has been left; and forming a transistor using the first gate insulator film, and a transistor using the second gate insulator film.
According to another aspect of the present invention, a semiconductor integrated circuit device comprises; a first gate insulator film formed on a semiconductor substrate of a first conductive type; a first semiconductor region which is formed on the semiconductor substrate and which includes an impurity of a second conductive type; a second annular semiconductor region which is formed on the semiconductor substrate and which includes an impurity of the second conductive type; a third embedded semiconductor region which is formed on the semiconductor substrate and which includes an impurity of the second conductive type; a fourth embedded semiconductor region which is formed in a region surrounded by the second annular semiconductor region and which includes an impurity of the second conductive type; a fifth embedded semiconductor region which is formed in the first semiconductor region and which includes an impurity of the second conductive type; a sixth semiconductor region which is formed above the third semiconductor region and which includes an impurity of the first conductive type; a seventh semiconductor region which is formed above the fourth embedded semiconductor region and which includes an impurity of the first conductive type; an eighth semiconductor region which is formed above the fifth embedded semiconductor region and which includes an impurity of the first conductive type; a second gate insulator film which is thinner than the first gate insulator film formed in the sixth, seventh and eighth semiconductor regions; a transistor using the first gate insulator film; and a transistor using the second gate insulator film.
In the semiconductor integrated circuit device with the above described construction, the third, fourth and fifth embedded semiconductor regions of the second conductive type are arranged below the sixth, seventh and eighth semiconductor regions. In addition, the second gate insulator film, which is thinner than the first gate insulator film, is arranged in the sixth, seventh and eighth semiconductor regions. Consequently, the mask used for introducing the impurity of the first conductive type for forming the sixth, seventh and eighth semiconductor regions, the mask used for introducing the impurity of the second conductive type for forming the third, fourth and fifth embedded semiconductor regions, and the mask used for removing the first gate insulator film can be in common with each other. Therefore, in the semiconductor integrated circuit device having the well (the eighth semiconductor region) of different conductive type from that of the substrate, the well (the sixth semiconductor region) which has the same conductive type as that of the substrate and which is connected to the substrate, the well (the seventh semiconductor region) which has the same conductive type as that of the substrate and which is pn-separated from the substrate, and various gate insulator films having different thickness, it is possible to suppress the increase of the number of photolithography steps.
According to another aspect of the present invention, a semiconductor integrated circuit device comprises: a semiconductor substrate; a first element region of a first conductive type defined in the semiconductor substrate by an element isolating insulator film; a second element region of the first conductive type defined in the semiconductor substrate by the element isolating insulator film, the second element region having a lower impurity density than that of the first element region; first and second transistors of a second conductive channel formed in the first and second element regions, respectively; and an element isolating layer of the first conductive type formed below an element isolating insulator film adjacent to the second element region of the semiconductor substrate, the element isolating layer having an impurity density substantially equal to that of the first element region and a depth substantially equal to that of the first element region from the substrate surface of the first and second element regions.
In this semiconductor integrated circuit device, the semiconductor substrate may have the first conductive type, the first element region may be defined, by the element isolating insulator film, in a first conductive type well formed by ion implantation before forming the element isolating insulator film, and the element isolating layer may be formed at the same time that an ion implantation step of forming the first conductive type well is carried out.
In this semiconductor integrated circuit device, the element isolating insulator film may be embedded in a groove formed in the semiconductor substrate.
In this semiconductor integrated circuit device, a third element region of a second conductive type defined by the element isolating insulator film may be formed in the semiconductor substrate, and a transistor of a first conductive channel may be formed in the third element region.
According to a further aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: forming an ion implantation mask having an opening in first, second and fourth predetermined regions of a semiconductor substrate, among the first predetermined region serving to form therein a first element region of a first conductive type, the second predetermined region serving to form therein an element isolating region adjacent to the first element region, a third predetermined region of the first conductive type serving to form therein a second element region having a lower impurity density than that of the first element region, and the fourth predetermined region serving to form therein an element isolating region adjacent to the second element region; ion-implanting an impurity into the semiconductor substrate via the opening of the ion implantation mask to simultaneously form a first conductive type well in the first element region and the element isolating region adjacent thereto, and an element isolating layer of the first conductive type in the element isolating region adjacent to the second element region; forming an element isolating insulator film in the element isolating region of the semiconductor substrate; and forming first and second transistors of a second conductive channel in the first and second element regions, respectively.
In this producing method, the semiconductor substrate may have the first conductive type, and the step of forming the first conductive type well and the element isolating layer may ion-implant an impurity of the first conductive type more deeply than a bottom of the element isolating insulator film formed thereafter.
According to a still further aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising: a step of forming a first ion implantation mask having an opening in first, second and fourth predetermined regions of a semiconductor substrate, among the first predetermined region serving to form therein a first element region of a first conductive type, the second predetermined region serving to form therein an element isolating region adjacent to the first element region, a third predetermined region of the first conductive type serving to form therein a second element region having a lower impurity density than that of the first element region, and the fourth predetermined region serving to form therein an element isolating region adjacent to the second element region; a first ion implantation step of ion-implanting an impurity into the semiconductor substrate via the opening of the first ion implantation mask to simultaneously form a first conductive type well in the first element region and the element isolating region adjacent thereto, and an element isolating layer of the first conductive type in the element isolating region adjacent to the second element region; a step of forming a second ion implantation mask having an opening in the third predetermined region of the semiconductor substrate; a second ion implantation step of ion-implanting a first conductive type impurity into the semiconductor substrate via the opening of the second ion implantation mask, at a lower dose than that of the impurity in the first ion implantation step, and more shallowly than the impurity in the first ion implantation step; a step of forming an element isolating insulator film in the element isolating region of the semiconductor substrate; and a step of forming first and second transistors of a second conductive channel in the first and second element regions, respectively.
In this producing method, the first ion implantation step may ion-implant the impurity of the first conductive type more deeply than a bottom of the element isolating insulator film formed thereafter, and the second ion implantation step is a channel ion implantation for controlling a threshold of the second transistor.
In this producing method, the step of forming the element isolating insulator film may have a step of forming a groove in the semiconductor substrate and a step of embedding an element isolating insulator film in the groove.
This producing method may further comprise the steps of: forming an ion implantation mask having an opening in a fifth predetermined region serving to form therein a third element region of a second conductive type and a sixth predetermined region serving to form therein an element isolating region adjacent to the third element region, before forming the element isolating insulator film; ion-implanting a second conductive type impurity into the semiconductor substrate via the opening of the ion implantation mask to form a second conductive type well in the third element region and the element isolating region adjacent thereto; and forming a transistor of a first conductive channel in the second conductive type well after forming the element isolating insulator film.
According to the present invention, the first and second transistors are formed in the first and second element regions which have the same first conductive type and different impurity density, respectively, whereas the element isolating layer of the first conductive type formed in the element isolating region adjacent to the second transistor formed in the second element region of the low impurity density has substantially the same impurity density as that of the first element region, in which the first transistor is formed, and has substantially the same depth from the substrate surface of the element region as that the first element region.
Specifically, this structure is obtained by forming the element isolating layer of the first conductive type in the element isolating region adjacent to the second element region at the same time that the ion implantation step of forming the well of the first conductive type in the region including the first element region is carried out, before forming the element isolating insulator film in the semiconductor substrate. Thus, the second transistor formed in the region of the low impurity density has excellent element isolation characteristics.
In addition, according to the present invention, since the ion implantation for the well of the first conductive type and the element isolating layer of the first conductive type is carried out before forming the element isolating insulator film, there is no step when the ion implantation mask is patterned by the resist. In addition, the thickness of the resist must not be so great unlike the ion implantation carried out after forming the element isolating insulator film. Therefore, it is possible to easily pattern the resist having the fine opening, and it is possible to surely form the element isolating layer in a narrow region via the obtained fine opening.